
`include "defines.v"

module data_mem (
    input  wire              clk,
    input  wire              rst,
     
    input  wire [`BUS_WIDTH] addr,
    input  wire [`BUS_WIDTH] mem_wdata,
    input  wire              mem_ren,
    input  wire [`BUS_WIDTH] mem_wmask,
    input  wire              mem_wen,
    
    output reg  [`BUS_WIDTH] mem_rdata
);
    
    
    wire [`BUS_WIDTH] rdata;
    
    RAMHelper mem(
        .clk   (clk),
        .en    (mem_ren | mem_wen),
        .rIdx  ({3'b0, ((addr - `PC_START)  >> 2'b11)}),
        .rdata (rdata),
        .wIdx  ({3'b0, ((addr - `PC_START)  >> 2'b11)}),
        .wdata (mem_wdata),
        .wmask (mem_wmask),
        .wen   (mem_wen)
    );

    assign mem_rdata = (rst) ? `ZERO_WORD : rdata;


endmodule
